When a 4-layer PCB starts running out of routing space, BGA fanout becomes difficult, power planes are heavily fragmented, or high-speed signals can no longer maintain a continuous reference plane, continuing to squeeze everything into four layers is often no longer the best option.
Moving to six layers provides more than two additional copper layers. More importantly, it gives designers room to reorganize the Signal, Ground, and Power layers so that high-speed routing, return paths, and power distribution are less likely to interfere with one another.
However, six layers also introduce new design questions.
How should L1 through L6 be arranged?
Is the common:
Signal / Ground / Signal / Power / Ground / Signal
suitable for every design?
If the finished board thickness is 1.6 mm, how should the dielectric thickness be distributed between layers? When designing for 50 Ω controlled impedance, can the same trace width be used for both outer- and inner-layer routing?
These are the questions that should be addressed early when planning a 6-layer PCB stackup.
What Changes When You Move from 4 Layers to 6?
A 6-layer PCB is a multilayer PCB with six conductive copper layers.
In terms of layer count, it has two more copper layers than a 4-layer board. From a design perspective, the greater benefit is the additional flexibility to combine Signal Layers and Reference Planes.
A common 4-layer structure is:
Signal / Ground / Power / Signal
This structure is sufficient for many conventional digital PCBs, but it provides only two primary signal layers. As BGA I/O counts increase, high-speed interfaces become more numerous, or a Power Plane is divided into multiple voltage regions, routing, reference planes, and power distribution can quickly begin competing for limited layer space.
With six layers, you can add internal routing capacity or dedicate the additional copper layers to Ground or Power. Critical high-speed signals can be placed closer to continuous reference planes, and BGA breakout has more available routing channels.
However, a 6-layer PCB does not automatically mean “four Signal Layers plus two Plane Layers.”
Some designs benefit more from an additional Ground Plane, while others require a dedicated Power Plane. The layer count provides flexibility; the final allocation should still be driven by the circuit requirements.
Is There a Standard 6-Layer PCB Stackup?
There are several common structures, but no single layer order is suitable for every PCB.
One common starting point is:
- L1 — Signal
- L2 — Ground
- L3 — Signal
- L4 — Power
- L5 — Ground
- L6 — Signal
In shorthand:
S / G / S / P / G / S
This is a well-balanced structure.
L1 can reference the L2 Ground Plane directly, and L6 can reference the L5 Ground Plane. The middle of the stackup provides an additional Signal Layer, while another layer is available for power distribution.
For digital PCBs using MCUs, FPGAs, MPUs, medium-complexity BGAs, Ethernet, USB, DDR, and similar interfaces, this can be a reasonable initial stackup to evaluate.
However, “common” does not mean “automatically correct.”
For example, although L3 is located between L2 Ground and L4 Power, the actual reference plane for a critical high-speed signal still depends on dielectric thickness and interlayer coupling. If L4 is divided into multiple power islands, it should not simply be treated as a continuous reference plane.
The key questions are which plane each critical signal references and how its return path is maintained.
Three Practical 6-Layer PCB Stackups
Different layer orders solve different problems. Instead of looking for a universal “best 6-layer PCB stackup,” it is more useful to understand which conditions each common structure is suited for.
Option 1: Signal / Ground / Signal / Power / Ground / Signal
The structure is:
- L1 — Signal
- L2 — Ground
- L3 — Signal
- L4 — Power
- L5 — Ground
- L6 — Signal
This is a balanced, general-purpose option.
L1 and L6 are both directly adjacent to Ground Planes, making them suitable for high-speed signals that are sensitive to reference-plane continuity. L3 provides additional internal routing capacity, while L4 is used primarily for power distribution.
L3 deserves particular attention.
If L3 is coupled mainly to the L2 Ground Plane, critical high-speed signals can use L2 as their primary reference. If L3 is also strongly influenced by L4 Power, you must verify whether L4 is sufficiently continuous and how high-frequency return current will reach Ground.
Although this structure is common, high-speed routing should still be planned according to the actual dielectric spacing and Power Plane segmentation.
Option 2: Signal / Ground / Power / Signal / Ground / Signal
The structure is:
- L1 — Signal
- L2 — Ground
- L3 — Power
- L4 — Signal
- L5 — Ground
- L6 — Signal
This arrangement places the Power Plane on L3 and uses L4 as an additional internal Signal Layer.
L1 references L2 Ground, while L4 can reference L5 Ground. This gives the two main high-speed routing regions relatively straightforward access to continuous Ground References.
The adjacent L2 Ground and L3 Power layers can also form a closely spaced Power/Ground plane pair. However, the amount of high-frequency decoupling benefit provided by plane capacitance depends on the actual layer spacing, overlap area, and dielectric properties. Simply placing Ground and Power next to each other does not guarantee strong performance.
This stackup is well suited to designs that require a dedicated Power Plane while still needing an internal high-speed Signal Layer.
Option 3: Signal / Ground / Signal / Ground / Power / Signal
The structure is:
- L1 — Signal
- L2 — Ground
- L3 — Signal
- L4 — Ground
- L5 — Power
- L6 — Signal
This structure places greater emphasis on Ground References.
L3 is located between two Ground Planes. If the layer spacing is designed appropriately, it can provide a relatively clean internal stripline routing environment. This can be advantageous for PCBs that need tighter control of crosstalk and EMI or that place sensitive signals on internal layers.
The bottom layer, L6, requires more caution.
Its nearest plane is the L5 Power Plane. If L5 is divided into multiple voltage regions, L6 is not an ideal location for a large number of critical high-speed signals. In practice, L6 may be better suited to low-speed signals, local power connections, or other nets that are less sensitive to reference-plane continuity.
The three options can be compared as follows:
| Stackup | Best suited for | Main advantage | Key consideration |
|---|---|---|---|
| S / G / S / P / G / S | General-purpose high-speed digital PCBs | Balanced routing, Ground, and Power allocation | The L3 reference relationship must be evaluated together with dielectric spacing and L4 continuity |
| S / G / P / S / G / S | Designs requiring a dedicated Power Plane and internal high-speed routing | L1, L4, and L6 can be placed close to Ground References | Power/Ground plane performance depends on actual spacing and overlap area |
| S / G / S / G / P / S | Designs that prioritize internal Ground References | L3 can provide a strong internal reference environment | L6 is adjacent to a Power Plane, so high-speed routing requires caution |
There is no universally optimal six-layer stackup independent of the circuit requirements.
Determine the Reference Planes Before Assigning Signal and Power Layers
When planning a 6-layer stackup, it is easy to start with an allocation such as:
> Three Signal Layers, two Ground Layers, and one Power Layer.
Only afterward do you consider which plane each signal should reference.
For high-speed PCBs, the more effective approach is usually the reverse.
First identify the signals that actually require control, such as high-speed clocks, DDR, USB, Ethernet, or other controlled-impedance nets. Then determine which layers are appropriate for those signals and whether the adjacent reference planes are continuous.
Key questions include:
- Which nets are critical signals?
- Which plane does each high-speed Signal Layer primarily reference?
- Is the Reference Plane continuous?
- Is the Power Plane significantly segmented?
- Does the Reference Plane change when a signal changes layers?
- Could adjacent Signal Layers create strong coupling?
For high-speed signals, having “a copper layer nearby” is not enough. The more important question is whether that copper layer can provide a continuous, low-impedance, predictable return path.
Ground Planes usually satisfy this requirement more easily. Power Planes can also participate in signal referencing and high-frequency return-current paths, but you must consider their high-frequency connection to Ground and whether the Power Plane itself is continuous.
How Should Return Current Be Handled When a Signal Changes Layers?
A 6-layer PCB will often have more layer transitions than a 4-layer board.
For example, a high-speed signal may transition from:
L1 → Via → L3
The Signal Via provides a path for the signal to move between layers, but the return current must also transition from the original reference environment to the new one.
Assume that L1 primarily references the L2 Ground Plane.
If L3 also primarily references L2 Ground, the reference transition is relatively straightforward. If the signal begins referencing another Ground Plane after changing layers, an appropriate Ground Stitching Via should be placed near the Signal Via so that high-frequency return current does not have to travel a long distance to connect between planes.
A reference transition between Ground and Power is more complicated.
If a signal moves from a layer referenced to Ground to a layer whose nearest reference is primarily a Power Plane, the high-frequency return current must find a low-impedance path between Power and Ground. This usually requires evaluating the nearby decoupling path together with the actual plane structure.
In practice, the safer approach is still to keep critical high-speed signals close to continuous Ground Planes whenever possible and minimize unnecessary reference changes.
For high-speed PCB layer transitions, consider both:
Signal transition + Reference transition
—not just the location of the Signal Via.
A Typical 1.6 mm 6-Layer PCB Stackup
A 1.6 mm finished board thickness is very common, which is why you will often see searches such as:
> 6 layer PCB stackup 1.6 mm
However, 1.6 mm defines only the approximate finished board thickness; it does not define the complete stackup.
To illustrate how the dielectric spacing might be distributed, consider this simplified symmetrical example:
| Layer-to-layer structure | Example dielectric thickness |
|---|---|
| L1 → L2 | Approx. 0.13 mm |
| L2 → L3 | Approx. 0.22 mm |
| L3 → L4 | Approx. 0.69 mm |
| L4 → L5 | Approx. 0.22 mm |
| L5 → L6 | Approx. 0.13 mm |
If all six copper layers are assumed to be approximately 35 μm for illustration, this geometry can approach a total board thickness of 1.6 mm.
This table is intended only to explain the relationship between layer spacing. It is not a production-ready material stackup.
In actual PCB manufacturing, the dielectric between L1-L2, L2-L3, and the other layer pairs is formed from specific Core and Prepreg constructions selected by the fabricator. The final pressed Prepreg thickness is also affected by glass style, resin content, and copper distribution.
Even if two PCB manufacturers both offer:
6 Layer / 1.6 mm / FR-4
their Core/Prepreg combinations, dielectric thicknesses, Dk/Df values, copper thicknesses, and 50 Ω trace widths may all be different.
For controlled-impedance PCBs, these actual manufacturing parameters are more important than the nominal “1.6 mm” board thickness itself.
Why Does a 6-Layer Stackup Need Mechanical Balance?
As the layer count increases, the mechanical balance of the stackup becomes more important.
A PCB experiences temperature changes during lamination, subsequent thermal processing, and assembly reflow. If the dielectric structure, copper thickness, and copper distribution differ significantly between the top and bottom halves of the board, it becomes more difficult to maintain balanced thermomechanical stress, increasing the risk of bow and twist.
When designing a 6-layer structure, review the top-to-bottom dielectric distribution, Copper Weight, Core/Prepreg combination, and whether large copper areas create a significant imbalance.
“Symmetrical” does not necessarily mean that every layer must be a perfect mirror image.
The actual stackup may still contain some asymmetry to meet impedance or routing requirements. The goal is to avoid unnecessary severe imbalance and allow the PCB fabricator to determine whether the material combination, board thickness, or copper distribution requires adjustment or copper balancing.
Thin boards, heavy copper, and large-format PCBs are generally more sensitive to these issues.
How Are Core, Prepreg, and Copper Arranged in a 6-Layer Board?
A conventional 6-layer FR-4 PCB is typically built by laminating multiple inner-layer Cores, Prepreg layers, and outer Copper Foils. However, there is no single construction that applies to every board.
Core
Core is a fully cured, copper-clad dielectric material.
In a 6-layer structure, a Core typically carries inner copper layers on both sides. Its thickness determines the dielectric spacing between those copper layers.
Prepreg
Prepreg bonds inner-layer structures to one another and bonds the outer copper foil to the inner stackup.
During lamination, the resin flows and cures to form the final dielectric layers. The finished thickness depends not only on the original material but also on the glass style, resin content, residual copper coverage, and lamination conditions.
This is why controlled-impedance designs should not be calculated solely from a nominal Prepreg thickness found online.
Copper Weight
A 6-layer PCB may use 0.5 oz, 1 oz, 2 oz, or other copper weights, depending on current requirements, thermal performance, trace width and spacing, and manufacturing constraints.
Increasing copper thickness generally reduces DC resistance and increases current-carrying capacity for a given trace width. However, it also affects etched trace geometry, minimum trace width and spacing, and controlled impedance.
If a PCB with an existing impedance design is changed from 1 oz to 2 oz copper, the original trace width and spacing should normally be reviewed.
How Do You Design Controlled Impedance on a 6-Layer PCB?
A 6-layer PCB provides good opportunities for controlled-impedance routing, but the phrase “6-layer board” alone cannot tell you how wide a 50 Ω trace should be.
Characteristic impedance is primarily affected by:
- Dielectric Thickness
- Material Dk
- Copper Thickness
- Trace Width
- Differential Pair Spacing
- Reference Plane
- Trace Geometry
- Solder Mask, which may affect outer-layer structures
A six-layer board also requires you to distinguish between outer-layer microstrip and inner-layer stripline structures.
Outer-Layer Microstrip
For example, L1 may reference the L2 Ground Plane.
The trace is located on the PCB surface. Part of its electromagnetic field is distributed through the PCB material, while another part is affected by the solder mask and the surrounding dielectric environment.
Inner-Layer Stripline
If L3 is located between two reference planes and the spacing to the upper and lower planes is designed appropriately, it can form a stripline or asymmetric stripline structure.
Its field distribution differs from that of a surface microstrip.
Therefore, even when the target impedance is the same:
The 50 Ω trace width on L1
and:
The 50 Ω trace width on L3
will usually not be identical.
A more reliable design flow is:
Define the target impedance → Confirm the PCB fabricator’s actual stackup → Calculate the initial trace width and spacing → Have the fabricator adjust for actual materials and manufacturing compensation → Use an impedance coupon or TDR verification when necessary
If the design includes DDR, PCIe, USB, Ethernet, LVDS, MIPI, RF, or other impedance-sensitive signals, the stackup should ideally be confirmed before large-scale routing begins.
When Should You Move from 4 Layers to 6?
Many projects do not start with a decision to use six layers. Instead, the need becomes apparent during the 4-layer layout process as routing space and reference-plane capacity begin to run out.
Common warning signs include:
- BGA escape routing has become extremely difficult
- The two primary Signal Layers remain congested
- Multiple controlled-impedance interfaces are present
- Power Planes must be heavily segmented to accommodate power distribution
- High-speed signals require frequent layer transitions
- It is difficult to preserve continuous Ground References for critical signals
- EMI/EMC debugging options are becoming increasingly limited
If staying with four layers requires excessive detours, overly aggressive trace-width or spacing reductions, or compromises to the Ground Reference, moving to six layers is often more practical than continuing to compress the existing structure.
The fabrication cost of a 6-layer board is generally higher than that of a 4-layer board of the same size and material system, but layer count is not the only project cost factor.
If a better stackup reduces layout risk, simplifies EMI debugging, and avoids repeated redesigns caused by structural limitations, adding two layers may reduce overall development cost and schedule risk.
When Are Six Layers Still Not Enough?
If the design includes a large FPGA, a high-pin-count BGA, multiple DDR/PCIe/Ethernet interfaces, high-speed differential links, and several power rails, the Signal, Ground, and Power layers in a 6-layer board may still compete for space.
The key question is:
> Am I sacrificing Reference Plane continuity or routing quality just to keep the design at six layers?
If the answer is yes, it is worth evaluating an 8-layer board.
Typical warning signs include:
- BGA breakout still requires extensive detours
- Multiple high-speed interfaces need dedicated routing channels
- More continuous Ground Planes are required
- Power distribution continues to conflict with high-speed routing
- High-speed Signal Layers must be placed adjacent to one another without sufficient isolation
The right layer count should reduce design difficulty, not force engineers to work around limitations created by the stackup itself.
Standard Stackup or Custom Stackup?
Many PCB fabricators maintain proven standard 6-layer constructions.
For conventional FR-4 boards, common finished thicknesses, and typical impedance requirements, starting with the fabricator’s Standard Stackup is usually the most practical approach.
A mature standard construction generally offers more stable material availability, better-established lamination parameters, more predictable lead times, and more historical manufacturing data.
A Custom Stackup becomes more useful when the project requires a special board thickness, low-loss laminate, specific Dk/Df values, unusual copper weights, tightly controlled plane spacing, or an RF/microwave structure.
Custom does not automatically mean more professional.
The more important criterion is whether the stackup can reliably meet the electrical requirements while remaining suitable for volume manufacturing.
Common Design Problems in 6-Layer Stackups
Treating an Online Standard Stackup as a Fixed Dimension
S / G / S / P / G / S describes the function of each copper layer.
It does not tell you the actual Core thickness, Prepreg thickness, Dk, copper thickness, or 50 Ω trace width.
Those parameters must ultimately be based on the actual production stackup.
Assuming the Reference Is Fine Because a Plane Is Nearby
The presence of a plane is only the first step.
For high-speed signals, you must also check whether the plane is continuous, whether it is heavily segmented, and whether the signal crosses a plane boundary.
A Power Plane in particular should not be assumed to provide the same straightforward return-current path as a solid Ground Plane simply because it is close to a Signal Layer.
Adding Only a Signal Via When a Signal Changes Layers
When a high-speed signal changes layers, its return-current reference environment may change as well.
If there is no nearby low-impedance connection between the new Ground Reference and the original reference plane, the return current may be forced to take a longer path, increasing loop area and EMI risk.
Whether a Ground Stitching Via is needed near the Signal Via should therefore be considered as part of the complete layer-transition design.
Routing 50 Ω Traces Before Confirming the Stackup
If the initial design assumes an L1-L2 dielectric thickness of 0.18 mm, but the manufacturer’s available standard construction uses 0.10 mm or 0.25 mm, the original impedance geometry may need to be changed substantially.
For controlled-impedance nets, confirming the stackup before finalizing trace geometry usually reduces rework.
Placing Two High-Speed Signal Layers Too Close Together to Gain Routing Space
If two adjacent Signal Layers are not separated by a plane and have a small dielectric spacing, layer-to-layer coupling and broadside crosstalk can increase.
If such a layer order is unavoidable, coupling can be reduced by increasing the spacing between the two layers where possible and by planning routing directions and region assignments carefully. Simply adding another Signal Layer does not automatically improve the design.
What Should You Confirm with the PCB Fabricator Before Layout Is Finalized?
For a conventional, low-speed 6-layer board, a mature Standard Stackup from the fabricator is often sufficient.
If the design involves high-speed signals, controlled impedance, special materials, or unusual copper weights, confirm the following before final routing and layer assignments are locked:
- Finished Board Thickness
- Copper Weight
- Laminate Material
- Dk / Df, when relevant to the design
- Core / Prepreg Construction
- Pressed Dielectric Thickness
- Impedance Targets
- Impedance Tolerance
- Minimum Trace / Spacing
- Via / Drill Requirements
- Stackup Symmetry
- Standard or Custom Construction
The later this information is confirmed, the more likely it is that completed impedance routing and layer assignments will need to be revised.
For a high-speed 6-layer PCB, the stackup is part of the layout architecture—not a manufacturing detail to be added after the Gerber files are complete.
FAQ
What Is a Standard 6-Layer PCB Stackup?
One common option is:
Signal / Ground / Signal / Power / Ground / Signal
In shorthand:
S / G / S / P / G / S
It can serve as a practical starting point for many digital PCBs, but it is not the only standard. The final layer order should be determined by high-speed signal references, power distribution, EMI requirements, and manufacturing constraints.
How Many Signal Layers Does a 6-Layer PCB Typically Have?
There is no fixed number.
Many common 6-layer structures use three Signal Layers and allocate the remaining layers to Ground and Power. Other designs may use more Signal Layers or add more Plane Layers to improve EMI performance and Power Integrity.
The allocation should be based on routing density and reference requirements rather than a predetermined ratio.
What Is the Best 6-Layer PCB Stackup?
There is no single best stackup for every design.
A suitable stackup should provide continuous reference planes for critical high-speed signals while also meeting routing-space, power-distribution, controlled-impedance, and manufacturing requirements.
Is a 1.6 mm 6-Layer PCB Stackup Fixed?
No.
The 1.6 mm value describes only the finished board thickness. Different PCB fabricators may use different Core, Prepreg, and copper-thickness combinations to achieve a similar final thickness.
For controlled-impedance designs, use the final production stackup confirmed with the fabricator.
Can a 6-Layer PCB Support 50 Ω Impedance?
Yes.
The actual 50 Ω trace width must be calculated from the dielectric thickness, Dk, copper thickness, reference plane, and whether the trace uses a microstrip or stripline structure.
A fixed trace width found online should not be applied to every 6-layer board.
Should You Choose a 6-Layer or 8-Layer PCB?
If a 6-layer board provides sufficient routing space, continuous Ground References, and reasonable power distribution, there is no need to move to eight layers simply to increase the layer count.
When a high-I/O BGA, multiple high-speed interfaces, and several power rails continually compete for layer space—and maintaining six layers requires sacrificing reference continuity or routing quality—an 8-layer design is usually worth evaluating.
Conclusion
The value of a 6-layer PCB is not simply that it provides two more copper layers for routing. Its greater benefit is the additional freedom to organize Signal, Ground, Power, and Reference Planes more effectively.
For many digital PCBs, Signal / Ground / Signal / Power / Ground / Signal is a practical starting point. However, the final layer order should always come back to a few specific questions:
- Which plane does each critical high-speed signal reference?
- Are the reference planes continuous?
- How will return current transition when signals change layers?
- Is the impedance structure based on the actual materials and dielectric thicknesses?
- Can the stackup be manufactured consistently?
If these questions are answered early in the layout process, a 6-layer board provides more than additional routing space. It provides a PCB architecture that is easier to control, validate, and manufacture.