CSP IC Substrate for Compact Chip-Scale Package Applications
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General Specification:
Number of Layers: Mainly 2 or 4 layers
Structural Features: Thin substrate core with blind and buried vias
Substrate Size: 4 × 4 mm to 19 × 19 mm
Finished Thickness: 0.1–0.4 mm
Line Width / Spacing: 25/25–50/50 μm
Bond Finger Pitch: 75–130 μm
Surface Finish: Soft Au / AFOP / OSP
Special Processes: TLP / Etch Back / VIP / VOP
SAYFU manufactures CSP IC substrates for compact semiconductor packages requiring thin substrate construction, fine-line routing, blind and buried vias, and tightly controlled bonding features.
Typical CSP substrate designs use 2- or 4-layer structures with finished thicknesses from 0.1 to 0.4 mm and line width/spacing from 25/25 to 50/50 μm. Surface finishes and special processes can be selected according to the package structure, bonding method, via design, and assembly requirements.
General Specifications
| Specification | Capability |
|---|---|
| Number of Layers | Mainly 2 or 4 layers |
| Structural Features | Thin substrate core, blind and buried vias |
| Size | 4 × 4 mm to 19 × 19 mm |
| Finished Thickness | 0.1–0.4 mm |
| Line Width / Spacing | 25/25–50/50 μm |
| Bond Finger Pitch | 75–130 μm |
| Surface Finish | Soft Au / AFOP / OSP |
| Special Processes | TLP / Etch Back / VIP / VOP |
CSP Substrate Manufacturing Capability
Thin CSP substrates combine compact package dimensions with fine routing and dense interconnect structures. Manufacturing these substrates requires precise control of line formation, via structures, bonding features, finished thickness, and dimensional stability.
SAYFU supports CSP substrate production with fine-line imaging, laser blind vias, copper-filled via structures, bond finger formation, and thin-core processing.
Our broader IC substrate capability includes BT materials from MGC, Doosan, LG, and AMC, with production line/space capability down to 25/25 μm by tenting, 15/15 μm by mSAP, and 13/13 μm by ETS. Production laser vias can reach 55 μm, while bond finger pitch can be manufactured down to 65 μm for designs requiring finer interconnection features.
The manufacturing process is selected according to the substrate stack-up, routing density, via structure, bonding method, and reliability requirements.
Fine-Line Routing and Via Structures
CSP designs often need to route multiple die-side connections through a very limited substrate area.
For this CSP substrate range, SAYFU supports 25/25–50/50 μm line width and spacing, together with blind and buried via structures for compact layer-to-layer interconnection.
For designs requiring higher routing density, laser microvias, copper-filled vias, VIP, VOP, and other IC substrate structures can be evaluated according to the package layout and stack-up.
Routing geometry is reviewed together with via pad dimensions, layer registration, finished thickness, and bonding layout so that individual design features remain manufacturable as part of the complete substrate structure.
Bond Finger Geometry
This CSP substrate range supports 75–130 μm bond finger pitch.
Bond finger pitch, width, spacing, surface finish, and opening geometry need to match the bonding process and package layout. These features are particularly important in wire-bond CSP designs, where consistent bond pad geometry directly affects assembly process stability.
For designs requiring finer bonding features, SAYFU’s broader IC substrate production capability supports bond finger pitch down to 65 μm.
Surface Finish and Special Processes
Available surface finishes include Soft Au, AFOP, and OSP.
The appropriate surface finish is selected according to the package structure, bonding method, interconnection requirements, and subsequent assembly process.
Special processes including TLP, Etch Back, VIP, and VOP are also available for substrate designs requiring specific via, routing, or bonding structures.
Surface finish and special-process requirements are reviewed together with the substrate drawing and stack-up before production.
Manufacturing Control for Thin CSP Substrates
Thin CSP substrates require tighter control of registration, thickness, via formation, and bonding features than conventional PCB structures.
Key manufacturing controls include fine-line registration, substrate thickness and flatness, blind and buried via integrity, bond finger geometry, surface finish consistency, and dimensional accuracy.
Different CSP architectures can also require different die-side interconnection structures. Wire-bond CSP and flip-chip CSP designs, for example, place different demands on routing, via layout, bonding features, and surface treatment.
For this reason, SAYFU reviews the actual substrate design, stack-up, routing dimensions, via structure, bonding geometry, and surface finish requirements before production.
Typical Applications
CSP IC substrates are commonly used in semiconductor packages where compact dimensions and high interconnection density are required.
Typical applications include:
- Memory devices
- RF and wireless devices
- Telecommunications electronics
- Microcontrollers and processors
- ASIC packages
- Smartphones and mobile electronics
- Compact digital and portable electronic products
CSP substrates are particularly suitable for designs where package size, routing density, weight, and overall package height are important considerations.
Send Us Your CSP Substrate Design
CSP substrate manufacturability depends on the complete package structure rather than any single parameter. Line width and spacing, substrate thickness, via construction, bond finger geometry, surface finish, and stack-up all need to work together.
Send SAYFU your substrate drawing, Gerber data, stack-up, via requirements, bond finger dimensions, surface finish requirements, and target quantity.
Our engineering team will review the design against the required manufacturing processes and prepare the project for quotation.