PBGA IC Substrate for Plastic Ball Grid Array Packages

SAYFU manufactures PBGA IC substrates for wire-bond semiconductor packages requiring multilayer routing, fine bond finger geometry, and reliable BGA interconnection.

For this PBGA substrate range, we support mainly 4-layer constructions, 0.4–0.6 mm finished thickness, 30/30–60/60 μm line width/spacing, and 100–140 μm bond finger pitch, with Soft Au and ENEPIG surface finishes available according to bonding and package requirements.

If your design requires tighter routing, finer bonding features, or a more complex multilayer structure, SAYFU can also evaluate it against our broader IC substrate manufacturing capabilities.

Send us your package drawing, Gerber data, ball map, or stack-up for a manufacturability review before quotation.

Send Your PBGA Substrate Design for Review

General Specifications

Specification	Capability
Number of Layers	Mainly 4 layers; higher-layer structures available according to design requirements
Structural Features	Multilayer laminate construction with through vias
Substrate Size	17 × 17 mm to 37.5 × 37.5 mm
Finished Thickness	0.4–0.6 mm
Line Width / Spacing	30/30–60/60 μm
Bond Finger Pitch	100–140 μm
Surface Finish	Soft Au / ENEPIG
Special Process	TLP

PBGA Substrate Manufacturing Capability

PBGA substrates need to route die-side connections to the solder-ball array within a limited package area while maintaining stable bond finger geometry, via connections, layer registration, and substrate dimensions.

SAYFU supports the key manufacturing processes required for these structures, including multilayer laminate processing, fine-line patterning, through-via interconnection, bond finger formation, and package-substrate surface finishing.

For PBGA designs requiring tighter features than the typical specifications above, our broader IC substrate capabilities include:

• Production line/space down to 25/25 μm with tenting
• Bond finger pitch down to 65 μm
• Laser via sizes down to 55 μm
• BT substrate materials from MGC, Doosan, LG, and AMC
• Additional fine-line processes including mSAP and ETS

These capabilities provide additional process margin when a PBGA design requires finer routing, tighter bonding geometry, or a more complex multilayer interconnection structure.

The actual manufacturing process is selected according to the package drawing, ball map, die size, routing density, layer structure, and reliability requirements.

Fine-Line Routing and Through-Via Structure

For this PBGA substrate range, SAYFU supports 30/30–60/60 μm line width and spacing, together with through-via interconnection between routing layers.

A typical 4-layer structure can accommodate many conventional PBGA designs. As I/O count, power distribution requirements, or routing density increase, additional layers may be required to provide sufficient routing channels.

During design review, we evaluate line/space, via dimensions, layer registration, routing around the bonding area, ball-map density, and finished substrate thickness together rather than checking each parameter independently.

This helps identify potential manufacturability issues before the design enters production.

Bond Finger Design for Wire-Bond PBGA

Bond finger geometry is one of the key areas in a wire-bond PBGA substrate.

This product range supports 100–140 μm bond finger pitch. During manufacturability review, SAYFU evaluates:

• Bond finger pitch
• Finger width and spacing
• Surface finish
• Opening geometry
• Routing around the bonding area
• Relationship between die position and bond finger layout

For designs requiring finer bonding features, our broader IC substrate production capability supports bond finger pitch down to 65 μm.

This gives additional flexibility when the package layout cannot be accommodated within standard PBGA bonding dimensions.

Soft Au and ENEPIG Surface Finish

Available surface finishes for this PBGA substrate include Soft Au and ENEPIG.

Soft Au is commonly used for wire-bond applications where a suitable bonding surface is required.

ENEPIG provides a nickel-palladium-gold finish and can be considered when the package requires both wire-bond compatibility and solderable surface characteristics.

The final finish should be selected according to the wire material, bonding process, package structure, and assembly requirements.

TLP Process

TLP is available for PBGA substrate designs requiring this plating process.

Because the plating method can affect routing geometry, bond finger design, and other substrate features, TLP requirements should be included in the project data at an early stage.

SAYFU reviews the plating requirement together with the substrate artwork, stack-up, and package drawing before production.

Manufacturing Control for PBGA Substrates

A PBGA substrate cannot be evaluated only by layer count or minimum line width. Several manufacturing features need to remain consistent across the complete substrate.

Key process controls include:

• Fine-line registration
• Layer-to-layer alignment
• Through-via integrity
• Finished substrate thickness
• Bond finger dimensions
• Surface finish consistency
• Solder mask registration
• Dimensional accuracy

For each project, these features are reviewed against the actual package structure to make sure the routing, bonding area, via structure, and ball-side interconnection can be manufactured together.

Why Work With SAYFU for PBGA Substrates?

IC Substrate Manufacturing Capability

PBGA projects are supported by SAYFU’s broader IC substrate manufacturing processes rather than being treated as standard multilayer PCB orders.

This includes thin laminate processing, fine-line patterning, bond finger manufacturing, laser via capability, and multiple package-substrate surface finishes.

More Process Margin for Difficult Designs

A typical PBGA project may use 30/30 μm routing and 100–140 μm bond finger pitch, while SAYFU’s broader manufacturing capability extends beyond these typical product specifications.

This allows our engineering team to evaluate designs that require finer routing, tighter bonding geometry, or more demanding interconnection structures.

Engineering Review Before Quotation

Before quotation, the design can be reviewed for key manufacturing requirements such as:

• Layer structure
• Routing density
• Via construction
• Bond finger geometry
• Surface finish
• Substrate thickness
• Package dimensions

The goal is to identify manufacturing constraints before the project moves further into production.

Typical Applications

PBGA IC substrates are commonly used for semiconductor devices requiring relatively high I/O density and a mature wire-bond BGA package structure.

Typical applications include:

• Microprocessors
• Microcontrollers
• ASICs
• DSPs
• Memory devices
• PC chipsets
• Graphics processors
• Communication ICs

The appropriate substrate structure varies with die size, I/O count, ball-map density, package dimensions, power distribution, and routing requirements.

 

Send Your PBGA Substrate Design for Review

Not sure whether your current PBGA substrate design fits a standard manufacturing process?

Send us the available project data. You do not need to prepare every item before contacting us.

Our engineering team can review the routing density, layer structure, bond finger geometry, via design, surface finish, and key manufacturing requirements before preparing the quotation.

Send Your Design for Review

Request a PBGA Substrate Quote